module  sin
(
    input   wire            sys_clk     ,   //系统时钟,50MHz
    input   wire            sys_rst_n   ,   //复位信号,低电平有效
    input                   digit_signal,
    output  wire    [7:0]   data_out        //波形输出
);


parameter   FREQ_CTRL   =   32'd42949   ,   //相位累加器单次累加值
            PHASE_CTRL  =   12'd1024    ;   //相位偏移量
			

parameter   FREQ_CTRL2   =   32'd85898   ;   //相位累加器单次累加值
parameter   PHASE_CTRL2   =   32'd2048   ;   //相位累加器单次累加值	
		
//reg   define
reg     [31:0]  fre_add     ;   //相位累加器
reg     [11:0]  rom_addr    ;   //ROM读地址	
wire    [7:0]   sin_out     ;


//reg   define
reg     [31:0]  fre_add2     ;   //相位累加器
reg     [11:0]  rom_addr2    ;   //ROM读地址	
wire    [7:0]   sin_out2     ;


assign data_out = (digit_signal)?sin_out:sin_out2;

always@(posedge sys_clk or negedge sys_rst_n)
    if(sys_rst_n == 1'b0)
        fre_add <=  32'd0;
    else
        fre_add <=  fre_add + FREQ_CTRL;	
       
      
always@(posedge sys_clk or negedge sys_rst_n)
    if(sys_rst_n == 1'b0)
        fre_add2 <=  32'd0;
    else
        fre_add2 <=  fre_add2 + FREQ_CTRL; 

//rom_addr:ROM读地址
always@(posedge sys_clk or negedge sys_rst_n)
    if(sys_rst_n == 1'b0)
        begin
            rom_addr        <=  14'd0;
        end
    else begin
		    rom_addr    <=  fre_add[31:20] + PHASE_CTRL;
	end
    
    
always@(posedge sys_clk or negedge sys_rst_n)
    if(sys_rst_n == 1'b0)
        begin
            rom_addr2        <=  14'd0;
        end
    else begin
		    rom_addr2    <=  fre_add2[31:20] + PHASE_CTRL2;
	end

rom_wave    rom_wave_inst1
(
    .address    (rom_addr   ),  //ROM读地址
    .clock      (sys_clk    ),  //读时钟

    .q          (sin_out   )   //读出波形数据
);

rom_wave    rom_wave_inst2
(
    .address    (rom_addr2   ),  //ROM读地址
    .clock      (sys_clk    ),  //读时钟

    .q          (sin_out2   )   //读出波形数据
);




endmodule